Sensitive imaging with large-format solid-state devices at high frame rates (˜1 million frames per second) is a difficult task. More specifically, a large-format solid-state imager with exposure times below a nanosecond do not exist. High-speed imaging is done either with film or specially adapted tube-based technology (streak cameras, intensified tubes, modified microchannel plates, etc.). These approaches typically suffer from low dynamic range, low contrast, high noise, and inflexible operation.
While conventional imager technology is appropriate for sub-microsecond integration times, the conventional pixel architecture makes it challenging to extend this technology to shutter times below a few nanoseconds. Moreover, for high-speed, large-format detectors with millions of pixels, the exposure control must be distributed to all pixels such that the sampling occurs effectively simultaneously. For detectors with dimensions of multiple centimeters, the time to propagate across a chip is hundreds of picoseconds. Thus, the control signal distribution system of conventional imager technology fails to provide an architecture to realize such fast shutter times.
Therefore it is desirable to provide a pixel architecture that is capable of shutter times below a few nanoseconds. Moreover, it is desirable to develop imager technology to provide x-ray imaging detectors with very high-speed sampling performance (100 picoseconds to 1 nanoseconds) for such applications as plasma diagnostics and high-speed radiographic imaging. Lastly, it is desirable to provide fast-sampling, large-format focal-plane arrays, which enable distribution of the signals that control the start and length of an integration period in a manner to realize shutter times below a few nanoseconds.